Fig. 1. Block diagram of a NAND flash memory. voltages for programming or erasing on chip. switch cir-cuits switch these high voltages into memory cell array via row decoder. Focusing on internal high-voltage ( ) switching and generation for low-voltageNAND flash memories, this paper de-scribes a switch, row decoder, and charge-pump circuit.
The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured. Construction. Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.